XC95144XL-5CS144C
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| Main description | CPLD XC9500 Family 3.2K Gates 144 Macro Cells 178.6MHz 0.35um, CMOS Technology 3.3V 144-Pin CSBGA |
CPLD XC9500 Family 3.2K Gates 144 Macro Cells 178.6MHz 0.35um, CMOS Technology 3.3V 144-Pin CSBGA
Informacje podstawowe
- ProducentXilinx
- EURoHSNo (2011/65/EU, 2015/863)
- Automotive No
Informacje dodatkowe
- Crosses 2
- Inventory 1
- PCNs 24
- MaskPart XC95144XL5CS144C%
- IntroductionDate May 01, 1996
Parametry
- Clock Management N/A
- Copy Protection Yes
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 3200
- Family Name XC9500
- I/O Voltage (V) 2.5|3.3
- In-System Programmability Yes
- Individual Output Enable Control Yes
- Maximum Clock to Output Delay (ns) 3.5
- Maximum Internal Frequency (MHz) 178.6
- Maximum Propagation Delay Time (ns) 5
- Maximum Storage Temperature (°C) 150
- Memory Size (Kbit) N/R
- Minimum Storage Temperature (°C) -65
- Number of Flip Flops N/A
- Number of Global Clocks 3
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers 4
- Number of Logic Blocks/Elements 8
- Number of Macro Cells 144
- Number of Product Terms per Macro 90
- Number of User I/Os 117
- Process Technology 0.35um, CMOS
- Program Memory Type Flash
- Programmability Yes
- Programmable Type In System Programmable
- RAM Bits (Kbit) N/A
- Reprogrammability Support No
- Speed Grade 5
- Supplier Temperature Grade Commercial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) 5
- Tradename XC9500