IS61C1024-12J

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Main description SRAM Chip Async Single 5V 1M-bit 128K x 8 12ns 32-Pin SOJ
SRAM Chip Async Single 5V 1M-bit 128K x 8 12ns 32-Pin SOJ

Informacje podstawowe

  • ProducentIntegrated Silicon Solution Inc
  • EURoHSNo (2011/65/EU, 2015/863)
  • Automotive No

Informacje dodatkowe

  • Crosses 651
  • PCNs 4
  • MaskPart IS61C102412J%
  • IntroductionDate Jun 22, 1999

Parametry

  • Address Bus Width (bit) 17
  • Architecture N/R
  • Data Rate Architecture N/R
  • Density (bit) 1M
  • Density in Bits (bit) 1048576
  • Function N/A
  • Maximum Access Time (ns) 12
  • Maximum Clock Rate (MHz) N/R
  • Maximum Operating Current (mA) 85
  • Maximum Operating Supply Voltage (V) 5.5
  • Maximum Operating Temperature (°C) 70
  • Minimum Operating Supply Voltage (V) 4.5
  • Minimum Operating Temperature (°C) 0
  • Number of Bits per Word (bit) 8
  • Number of I/O Lines (bit) 8
  • Number of Ports 1
  • Number of Words 128K
  • Supplier Temperature Grade Commercial
  • Timing Type Asynchronous
  • Typical Operating Supply Voltage (V) 5
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