EPM240GT100I5N
| Do pobrania | Download |
|---|---|
| Main description | CPLD MAX® II Family 192 Macro Cells 201.1MHz 0.18um Technology 1.8V 100-Pin TQFP Tray |
CPLD MAX® II Family 192 Macro Cells 201.1MHz 0.18um Technology 1.8V 100-Pin TQFP Tray
Informacje podstawowe
- ProducentIntel
- EURoHSYes (2011/65/EU, 2015/863)
- Automotive No
Informacje dodatkowe
- Crosses 237
- Inventory 3
- PCNs 56
- GIDEP-Alerts 3
- MaskPart EPM240GT100I5N%
- IntroductionDate Dec 21, 2004
Parametry
- Clock Management N/A
- Copy Protection Yes
- Data Gate No
- Device Logic Cells 240
- Device System Gates N/A
- Family Name MAX® II
- I/O Voltage (V) 1.5|1.8|2.5|3.3
- In-System Programmability Yes
- Individual Output Enable Control Yes
- Maximum Clock to Output Delay (ns) 6.9
- Maximum Internal Frequency (MHz) 1879.7
- Maximum Propagation Delay Time (ns) 7.5
- Memory Size (Kbit) 8
- Number of Flip Flops N/A
- Number of Global Clocks 4
- Number of I/O Banks 2
- Number of Inter Dielectric Layers 6
- Number of Logic Blocks/Elements 24
- Number of Macro Cells 192
- Number of Product Terms per Macro N/A
- Number of User I/Os 80
- Process Technology 0.18um
- Program Memory Type Flash
- Programmability Yes
- RAM Bits (Kbit) N/A
- Reprogrammability Support No
- Speed Grade 5
- Supplier Temperature Grade Industrial
- Temperature Flag Jun
- Tolerant Configuration Interface Voltage (V) 1.8|2.5|3.3|5
- Tradename MAX